CUCPS Talk on the P850 minicomputer. ------------------------------------ When you think of the early 70's minicomputers, the company that instantly springs to mind is DEC (Digital, call them what you will). Everybody has heard of, or even used the PDP8 and PDP11. When you think a little harder, you remember some other companies, like Hewlett-Packard, Data General, IBM and maybe Computer Automation. But one company that seems to have been forgotten in this contex is Philips. But Philips certainly made minicomputers - there's one here *** Point to the P850 *** If that machine hadn't existed, not only would I have had nothing to talk about tonight, but CUCPS may not have been founded. I'd like to tell you that story first. It all started 12 years ago in 1986. I was an undergraduate at Peterhouse, and I was designing a computer system. Now, back then, designing a computer meant buying a pile of chips and soldering them together. And some parts, like keyboards, were very expensive if bought new - you couldn't pop in to the local PC shop and buy a clone keyboard for a few tens of pounds. So when I saw this advert in Wireless World, I decided to go along and buy a keyboard *** Put up the Wireless World Advert *** Well I bought one. But I also saw this P850 being sold essentially as scrap metal. Well, it looked far too interesting for that, so I bought it. I then had to get it home. Fortunately there was a taxi company nearby, so I went to them, and in my typically insane way, I asked for 'A taxi with a boot large enough to put a mini in'. Well, after the strange looks and laughter had died down, I did indeed get a taxi, and I did get the machine back to my room That evening, while playing with it, I realised that unless something was done - and at once - a lot of computer history was going to be lost. Now, this was before the CCS, before CUCPS, so I had to do something myself. One thing led to another, and I started saving all the old computer hardware that I could. I also infected my friends, some of whom are here, with the same interests, and in the end, 10 years later, CUCPS was founded. So, that's why the P850 has a special interest to me. But what about the machine itself - what was it like to use and to program. And what was it like inside? The easiest way to explain how to use it is to describe the controls on the front panel. I'll point them out both on the machine and on this overhead of the front panel. **** Put up picture of the P850 panel *** The most obvious feature is the 16 toggle switches here, which have 16 lamps aboce them. It's a 16 bit machine, at least to the programmer, and these switches allow you to load a register or memory location. Somewhat unusually, bit 0 is the most significant bit. **** Demonstrate loading register 1 **** To the right of these switches are 4 buttons that select one of the 16 CPU registers. Register 0 is the program counter and register 15 (or B7) is the hardware stack pointer. Apart from that, all the registers are equivalent. You select a register using the obvious binary code *** Demonstrate that ***** The 5 buttons here select one of 4 modes - the 5th button is not used. They are : Load (to store data into a register or memory) Read (to display the contents of memory) Inst (single-step a program one instruction at a time) Run (Execute program) Finally, these 3 buttons select either a register (which is what I've been showing you up until now), the porcessor status, or the main memory. Accessing memory is somewhat odd, since there's no frontpanel address register. You use the program counter for that - to read memory, you load the start address into the PC, switch to memory, and step through it using the Start button. **** Demonstrate that *** Loading memory is similar, but it's better to explain the instruction set first, since then I can load a useful program into the machine. Here's a handout which gives the machine's instruction set *** Hand it out *** For those of you who like RISC instruction sets, this one should look very familiar. As can be seen from the next overhead, there are 2 basic instruction formats, distinguished by the state of bit 0. : **** Put up the instruction format overhead **** All instructions have an opcode as bits 1-4, and the opcodes are similar between the 2 types of instruction. Format 0 instructions only use a single register, which is selected by the 3 bit field 5-7. Only the first 8 registers can be used. The remaining 8 bits of the instruction can contain a constant, or another parameter for the instruction. Format 1 instructions normally specify 2 operand instructions, like AD. The first operand is given by the R1 field - all 16 registers can be used. The second operand can either be the contents of the register given by the R2 field, or that register can be used to provide a memory address, possibly indexed or indirected. How it is used is specified by the addressing mode field here. The final bit (15) determines where the result should go - into a register, or back to memory. Note that there are no immediate or direct addressing modes at the hardware level. You get those like you do on the PDP11 - by specifying the PC (0) in the R2 field. Unlike the PDP11, there are no autoincrement modes, but there's a couple of gates in the CPU that detect the PC is being used here and cause it to be incremented when necessary. There are a few special instructions that use some of the fields for other purposes, but all of them essentially fit one or other of the 2 patterns. This means that the instruction decoder in the CPU is quite simple. Here's a trivial little program that I wrote to add 2 numbers. **** Put up the overhead of that program ****. If I toggle it in like this. *** Do so *** And the run it. **** Press RUN and START **** we get the right answer in the register **** Show it **** OK, so that's how to use the machine. But what's inside it? It wouldn't be an ARD talk if I didn't pull the machine apart, so here goes : **** Turn the machine round and pull the PSUs **** The power supplies are simple linear units, and aren't very interesting. **** Pull one of the core units **** This block is 1K bytes of core memory. If I have time at the end I'll dismantle this for you and show you the core plane and the drivers. Now for the CPU itself. It's the top 5 boards in the top rack. Here's a block diagram of the machine. If I pull the ALU board, you'll notice that there are only 2 ALU chips on it. Each one is 4 bits wide. But this is a 16 bit machine isn't it? **** Put up the CPU block diagram from the service manual (fig 1.1) **** The first thing to notice is that internally it's an 8 bit machine - all the main buses are 8 bits wide. Just about the only 16 bit part is the I/O bus. That means there's no way an instuction can execute in a single cycle - even fetching an instruction from memory takes 2 cycles - the memory data bus is also 8 bits wide. Most cycles come in pairs, the first one for the low byte and the second one for the high byte. Now, lets look at the cycle flowchart of the processor. It's given in the service manual, and here it is : **** Put up the sequence of cycles ****** That register+register ADD instruction that we used earlier has the following sequence : F1, F2, E1, E2, L, and the path followed is this one *** Trace out the path on the OHP ****** Now, each machine cycle corresponds to 8 clock pulses - or t-states, and therefore, many different things happen Here's a rather complex diagram of what happens in the F0 cycle : **** Put up fig 1.4 from the technical manual **** The top part of the logic updates the program counter (register 0, of course) in the scratchpad. You can ignore the numbers like A7, T8, etc. Those simply give the pages where you find the schematic diagrams for that section. The numbers in the little boxes here tell you the t-states where the logic is used. The PC is updated in t-states 2 and 6. (Describe this in more detail if there's time). The low byte of the instruction is latched at t-state 2, and the LSB of the memory address is set at t-state 6. All the other cycles are similar, but don't worry, I'm not going to go through all of them. Now, those of you who've endured my previous talks on CPU design are now going to expect me to produce a microcode listing, and waffle on about control stores and fork logic. Well, I can't. This processor has no microcode. Let's go back to that flowchart again ***** Put fig 1.2 back up ***** Can any of you think of an alternative way to implement this sequence? Right, a state machine. There is a d-type flip-flop (you do all know what a d-type is, right? {If not, panic and explain it}) for each cycle type. One of them is set at a time, and there's some logic to control the sequence. There's also a Transfer Pulse signal, TFP, that occurs at the end of each cycle which clocks the logic Here's the logic for the fetch cycles : ******* Put up diagram T12 **** OK. An F1 cycle comes after an L cycle, provided certain conditions are met - detected by these gates. And after an F1 cycle, we get an F2 cycle - here... Now, a slightly more complex example - when do we get index cycles ? **** Put up diagram T4 ***** Well, the first index cycle follows an F2 cycle, look, if bit 9 of the instruction is set. That's the Index bit in the addressing mode field. XEC is just a signal which is deasserted if a conditonal branch fails. Then an X2 cycle follows an X1 cycle. Hang on, though... Haven't I missed something here? A format 0 instruction could have bit 9 set as part of the constant. Surely it doesn't do an index cycle, does it. No, of course not. And yet I spent a long time trying to figure out _how_ it avoided it. None of the input signals to that gate {point to X02/B5} depend on the top bit of the instruction register. *** Put up T12 again *** The answer also explains another feature that I glossed over. The F2 flip-flop is cleared as soon as the machine goes into the E1 state. But why? There's no way the machine can go into the E1 state from the F1 state, so surely this gate isn't necessary... Oh yes it is. If we look at the Execute diagram ***** Put up T6 ***** OK, it's complicated. But I'm not going to explain all of it - jsut one odd feature here {Point to the Async set to E07/E9). All Format 0 instructions assert the MREF signal. So, in state T3, half way through the F2 cycle, the set input here is asserted, and the machine goes into the E1 cycle, and executes t-state 4-7 of that cycle. Of course as soon as it gets into the E1 cycle, the F2 flip-flop is cleared as I just mentioned. And that means that F2 is not asserted at the same time as the Transfer Pulse in these instructions. So the Index cycle can never start. I could obviously go on for a long time about this machine and its control system, but I think I'd better leave it there and briefly mention a much later machine in the range - the P851. Unfortunately I can't show you one of those because I don't have one. In fact, I'm not sure if any still exist. But at least I have the manual for it. The processor fits on a single double-height Eurocard PCB. It can take up to 64K bytes of memory (MOS RAM, which is battery backed) - all the bits of the memory address are now used. This CPU is microcoded. This page from the service manual shows the microcode ROMs and the sequencer. **** Put up P851 fig 5-23b **** There's a fairly conventional microcode program counter here. This device - PLANET - is a custom chip that handles the microcode branch logic, and other functions *** Put up P851 5-23a **** The ALUs are also custom chips - 4-bit wide slices called SPALU. They contain much of the data path of the machine. There is a microcode flowchart in the manual, but I don't think we have time to go through all that tonight. Finally, I'd like to mention that these machines are not at all common. There is this P850, another one in the Dutch Computer Museum, and a larger machine in the same family called the P856 in Zurich. As far as I know, that's it. If any of you ever seen any P850-series parts for sale, you should buy them. Thank you.